Parent Category: 2017 HFE

*By NI/AWR*

**Overview**

It is widely held that S-parameters combined with harmonic balance (HB) alone cannot provide for the simulation of the power performance of transistors. This article describes a method for designing and simulating amplifiers within NI AWR Design Environment™ for maximum power using HB simulation when the only available data is the S-parameters of the transistors. The method is widely applicable when nonlinear transistor models are not available and can also be very helpful even when the nonlinear models are available.

The topic is an extension of Steve Cripps’ Load-Line Approach[1-3], which was developed further with the power parameters introduced by Pieter Abrie[4]. These techniques may be used to create useful approximations that allow HB simulation with transistors that do not have nonlinear models.

**A Recap of Cripps’ Load-Line Approach**

Figure 1 shows the output and load-line plot for a power amplifier (PA), along with expressions for the relationships between voltage, current, load, and power.

Figure 1 • Output and load-line plot for a power amplifier.

Figure 2 shows plots that illustrate the process of obtaining R_{opt }from load-line data, expanding on Figure 1 with Smith chart representations. Measured results are overlaid on the computed values, showing very good agreement.

Figure 2 • Plots illustrate the process of obtaining R_{opt} from load-line data. Measured results are overlaid on the computed values, showing very good agreement.

Cripps’ original paper was published in 1983 when HB simulation was not in use yet and load-pull measurements were the only option available for device characterization. When the technical note[2] was published, HB simulations were available but were, among other problems, very slow. The Cripps Approach, therefore, offered a much simpler way to design for high power.

Unfortunately, his approach was never implemented in any of the general simulators. It was, however, implemented in a more advanced form in the specialized MultiMatch Amplifier Design Wizard[5] developed by Pieter Abrie. Abrie presented the power parameters in his book and implemented them in MultiMatch for the design of Class A and Class AB amplifiers.

The mapping functions of the power parameters lifted any restrictions associated with the transistor’s configuration, including feedback, resistive loading, grounding node position, parallel chips/cells, reference plane issues, multistage, and more. There are interesting similarities with the noise parameters, such as series feedback, which allows for easier match for maximum power.

Today HB simulations are as fast as linear simulations were 20+ years ago. While accurate nonlinear transistor models have been developed, they are still not provided for many useful transistors. Abrie’s power parameters approach is a fully developed method that can easily be incorporated in any of the general simulators to speed up and enhance the design process for P_{1dB, }Psat _{max,} and more, especially when nonlinear models are not available.

**Design Example for a 0.5-2.5 GHz PA**

The streamlined design process[6] for the design of a 0.5-2.5 GHz stage with a 45 W gallium nitride (GaN) high-electron mobility transistor (HEMT) is described in this design example. In addition to the design process, the results of the HB simulations of the dynamic load lines (DLLs) for each stage will be shown. This will enhance the understanding of the design process and will also show a way of extracting the desired power from a transistor stage when a nonlinear model is not available.

Figure 3 shows a schematic in the Microwave Office circuit simulator in which the nonlinear model of the transistor and the tuners could be used to extract the impedances for the maximum power and gain over the frequency band. Instead only the S-parameters at transistor Imax/2 are extracted.

Figure 3 • Microwave Office schematic.

The extracted S-parameters are then imported into MultiMatch, where a linear model is fitted to them (Figure 4).

Figure 4 • Fitting a linear model to S-parameters in MultiMatch.

After defining the maximum current and voltage areas (clipping boundaries) on the I/V-curves, the power parameters are used to extract the load-pull data (Figure 5).

Figure 5 • Load-pull contours across the bandwidth.

In Figure 6, the output network is synthesized to provide the load impedance associated with the maximum pre-clipped power. This is followed by synthesis of the input lossy and lossless matching networks to provide maximum ﬂat gain and stability.

Figure 6 • MultiMatch layout of the network.

The MultiMatch layout is easily manipulated to the desired form and then with a few clicks the schematic and the layout are exported into Microwave Office (Figure 7).

Figure 7 • The equivalent layout in Microwave Office

In Microwave Office the microstrip discontinuities are fully simulated, either by electromagnetic (EM) models or full EM simulation of parts of the layout. The nonlinear model and the HB simulation are used to simulate the power levels of fundamental and harmonic signals, the associated gain and gain compression, currents and voltages, efficiency, and more. Using these simulations some small adjustments would usually be done to achieve the best possible performance.

**The Dynamic Load Line (DLL) in HB Simulation**

Cree provided the nonlinear models with access to the voltage and current across the intrinsic generator. The simulation of the voltage and current, and hence the DLL across the intrinsic generator, provided a much higher level of visualization, understanding, and design capabilities. Figure 8 shows the simulated DLLs across the bandwidth for Class A and Class AB biasing at low power levels. It is obvious that the Class A biasing provides maximum swing of the voltage and current and hence maximum Psat.

Figure 8 • The simulated dynamic load lines across the bandwidth for Class A and Class AB biasing at low power levels.

Figure 9 shows the DLLs at Psat of Class A and Class AB (left) and Psat and PAE across the bandwidth for Class A and Class AB (right). It is obvious that they are about the same for the two kinds of biasing, which illustrates the validity of the design method.

Figure 9 • DLLs at Psat of Class A and Class AB (top) and Psat and PAE across the bandwidth for Class A and Class AB (bottom).

In this example, two copies of the designed stage were connected with hybrid couplers to form a balanced output stage. Two consecutive driver stages were designed next. These stages are based on a Cree GaN HEMT, for which a nonlinear model is available, and a gallium arsenide (GaAs) heterojunction field-effect transistor (HFET), for which only S-parameters at a Class A biasing point are available.

The S-parameters of the GaN transistor extracted in Microwave Office and the S-parameters of the GaAs transistor were used in MultiMatch to create linear models for these transistors. With the voltage and current boundaries defined, the power parameters and the synthesis facilities were used to design the two driver stages to provide maximum power and ﬂat gain across the bandwidth. The simulated results of the MultiMatch design are shown in Figure 10.

Figure 10 • The simulated results of the MultiMatch design: gain and RL (left graph) and pre-clipped power for each stage and the full amplifier (right table).

In Figure 11, Stage 1 is the output stage and Stage 2 is the input stage of this two-stage driver. The S-parameters of the two transistors were replaced with the nonlinear model for the Cree GaN transistor and the linear model for the GaAs HFET. Voltage and current meters were placed across the intrinsic generators and an M-probe was placed at the output of the GaAs transistor.

Figure 11 • Driver schematic in Microwave Office.

In Figure 12 the nonlinear model was used to simulate the I/V-curves and the DLLs of the GaN transistor stage across the bandwidth. Also superimposed over them in the lower left corner are the boundaries that define the pre-clipped maximum voltage and current swings of the GaAs transistor. The DLLs are shown inside these boundaries. These load lines were simulated by using the HB simulator and the linear model of the transistor. The input power levels were selected/tuned so that the DLLs of the GaAs transistor stage just reached the hard clipping boundaries.

Figure 12 • Driver IV curves and DLLs.

From Figure 12 it can be seen that when the GaN transistor is already in deep compression the GaAs transistor has just started to compress. The pre-clipped output power is typically 0.5-1 dB below P_{1dB}. From this, it is obvious that the GaAs stage has sufficient power to drive the GaN stage.

Figure 13 shows the overall power gain, input RL and the overall output power and also the power at the output of the GaAs transistor measured by the M-probe in Figure 11.

Figure 13 • Power and gain performances of the 2-stage driver.

The linear model of the GaAs transistor was extracted from the S-parameters in a special facility in MultiMatch. It is also possible to do this in Microwave Office. For the GaAs transistor the only data available was the S-parameters, and after using them to extract a linear model, the HB simulation was used to simulate and predict the pre-clipped maximum output power (Class A).

This method of simulating the DLL and the pre-clipped output power is also very useful when it is important to provide proper loading to each cell of a multi-cell transistor, or when multiple transistors are connected in parallel, as is typically done in microwave monolithic integrated circuit (MMIC) PAs. Optimization for the correct DLL is much faster when linear models are used. This is important because the networks are typically very complex and the input networks also need to be optimized to provide equal drive.

Typically, the MMIC design kits provide linear and nonlinear models. Optimizing the initial circuit by using the linear models and then only checking the final results by using the nonlinear models provides for a better and faster, and, arguably, a more accurate design approach. The optimum load-line for maximum output power can also be optimized relatively quickly using the nonlinear model of the transistor if the input power for the simulation is low.

The method of HB simulation of the DLL using the linear model could also be used to extract the optimum load impedance for maximum output power of Class A amplifiers and, arguably, Class AB amplifiers. Figure 14 shows a schematic with which this could be done. It uses a linear transistor model driven by tuneable power source, an impedance tuner at the output, and a Gamma probe to place the impedance of the tuner on the Smith chart.

Figure 14 • Optimum load impedance extraction schematic.

Figure 15 illustrates the process of extracting the optimum load impedance. Impedances for any other power below the maximum can also be found. Extracting full load-pull data and contours is nearly instantaneous with the power parameters in MultiMatch.

Figure 15 • The process of extracting the optimum load impedance, with tuning for optimum DLL (left) and the load impedance corresponding to the optimum DLL (right).

Let’s not forget what happened with the design of the amplifier discussed earlier. The results of the final design are presented in Figures 16, 17, and 18.

Figure 16 • Photo of the resultant 0.5-2.5 GHz 50 W amplifier.

Figure 17 • The simulated small-signal and large-signal power gain (left) and the measured small-signal and large-signal power gain (right).

Figure 18 • The simulated Psat (left) and the measured Psat (right).

**Conclusion**

A method has been described for designing and simulating amplifiers for maximum power using HB simulation within Microwave Office when the only available data are the S-parameters of the transistors. The method is widely applicable, from low-noise amplifiers to high-power amplifiers and from narrowband to multi-octave bandwidth amplifiers. It is also useful anywhere where it is important to know, and design for, the power deliverable by any of the stages of an amplifier when nonlinear transistor models are not available. This method can also be very helpful even when the nonlinear models are available.

Pieter Abrie’s power parameters approach is a fast and versatile method, but it exists only in MultiMatch Amplifier Design Wizard. If the power parameters method is incorporated in the general simulators it will complement the described above method and, in general, dramatically enhance the design of RF/microwave amplifiers. While it is desirable to incorporate the power parameters in general-purpose simulators, the MultiMatch synthesis techniques and procedures are also required. These are the only real-frequency and real-world synthesis techniques available in a commercial software product. Their incorporation will provide unprecedented levels of productivity and creativity in the design of matching networks from inside the general simulators.

The recently-developed nonlinear models from Cree provide access to the voltage and current across the intrinsic generator. It is obvious that this opens up a much deeper level of insight and adds more versatility to design methods and approaches. Hopefully, this capability will be offered by all providers of linear and nonlinear models for RF/microwave transistors.

**References**

1. Cripps, S.C., “A Theory for the Prediction of GaAs Load-Pull Power Contours”, IEEE-MTT-S Int’l. Microwave Symposium Digest, 1983, pp 221-223.

2. Steve C. Cripps, “GaAs FET Power Amplifier Design”, Matcom, Inc., Technical Note 3.2

3. Cripps, S.C., RF Power Amplifies for Wireless Communications, Artech House, 1999, ISBN 0-89006-989-I.

4. Abrie, Pieter L.D., Design of RF and Microwave Amplifiers and Oscillators, Artech House, 2009, ISBN 978-1-59693-098-8

5. MultiMatch Amplifier Design Wizard, Pretoria: Ampsa (Pty) Ltd.; http://www.ampsa.com.

6. Ivan Boshnakov, Anna Wood, Simon Taylor. “RF & Microwave Solid State Power Amplifier Design is a Speciality”, ARMMS, April 2012