Parent Category: 2017 HFE
By David Vye
Next-generation wireless devices, LTE-A/5G infrastructure, and aerospace/defense electronic systems are creating new challenges for the way engineers design and develop RF/microwave products. These challenges, stemming from high performance goals for bandwidth, linearity, and efficiency, are complicated by system and market requirements for smaller, lighter, and less costly devices. In addition to engineering challenges, business concerns include escalating development costs, limited engineering resources, and time-to-market pressures.
To fulfill product requirements, new semiconductor and printed circuit board (PCB) materials, as well as module technologies, are being developed to achieve unprecedented integration and functionality within an increasingly smaller form factor (Figure 1).
Figure 1 • Module technologies are being developed to achieve unprecedented integration and functionality within a smaller form factor.
To successfully implement these technologies, engineers require highly automated simulation software that can accurately predict electrical performance as it relates to physical design that includes excitations and measurements associated with complex waveforms used in communication and radar systems as well as support for manufacturing processes.
V13, the latest release of NI AWR Design Environment, addresses these requirements with an integrated, open platform offering system, circuit, and EM co-simulation that captures the behavior of RF font-end components such as antennas, amplifiers, filters, mixers, and related signal-controlling passive and active devices. The latest enhancements improve engineering productivity with faster, more powerful circuit/system/electromagnetic (EM) technologies, robust model libraries, and greater design flow automation, supporting product development of microwave monolithic integrated circuits (MMICs), RFICs, RF PCBs, and multi-technology modules.
Design Environment and Automation
Design for Manufacturing
At RF and microwave frequencies, electrical performance is directly influenced by physical design. Therefore, great care must be taken to ensure that a component’s physical attributes are fully incorporated into the simulation model and that the physical details used in simulation are fully and accurately replicated by the manufacturing process. V13 offers new and improved features that impact design layout and interoperability between NI AWR Design Environment and third-party IC and PCB electronic design automation (EDA) tools (Figure 2).
Figure 2 • New PCB import wizard automates interoperability between NI AWR Design Environment and enterprise PCB layout tools.
These enhancements deliver key capabilities for design entry (both schematic and layout), parameterized circuits, systems, and EM subcircuits, design synthesis, simulation and optimization controls, and measurement graphs. Overall the improvements serve to better facilitate designs based on specific manufacturing processes such as PCBs and multi-technology (mixed-technology) projects, commonly used to simulate multi-chip modules (MCM) that incorporate diverse MMIC and RFIC devices on a single laminate package/module.
A process design kit (PDK) helps manage design entry with information that contains files for the device library (symbols, device parameters, PCells), technology data (layer stack ups), simulation models, verification deck, and more. PDKs are used by circuit designers to construct a simulation version of their product from these components made available through the fabrication process. In V13, PDK-specific improvements make it easier to install new PDKs and work with multiple layout process files (LPFs) typical of MCMs. Custom toolbars can now also be distributed in PDKs to support highly customized design flows for leading front-end manufacturers.
Embedding RFIC design in MCM simulations
With MCMs, the off-chip design and simulation including embedded passives and laminate interconnects often require some representation of the RFIC device(s) for the overall module characterization. Module designers need a way to incorporate an accurate model for the RFIC (or critical portions of the RFIC design) within the circuit hierarchy that includes the laminate substrate. Advances in hierarchical design management, complemented with a new OpenAccess import/export wizard (supporting, for example, the import/export of RFIC schematics and project symbols from Cadence Virtuoso) for Cadence Spectre netlist co-simulation, provide for the easy incorporation of small-scale RFICs developed in Cadence tools within an NI AWR Design Environment MCM analysis. With accurate RFIC blocks in the circuit hierarchy, MCM designers can focus on modeling and optimizing details of the laminate itself using 3D planar and/or full 3D EM simulation (AXIEM and Analyst™ respectively) or another third-party EM solver.
EM Simulation and Modeling
Native 3D Planar and Full 3D EM Solvers
AXIEM and Analyst EM simulators within NI AWR Design Environment use Maxwell’s equations to compute the electrical behavior of a structure from its physical geometry. AXIEM provides responses for 3D planar structures such as transmission lines, spiral inductors, and metal-insulator-metal (MIM) capacitors, whereas Analyst addresses 3D objects such as wire bonds, ball grids, finite substrates, and 3D horn antennas. Improvements to AXIEM and Analyst in V13 focus on solver speed and accuracy, as well as features that support greater automation and design flow integration with Microwave Office.
AXIEM V13 simulations using the iterative matrix solver are now faster due to the simultaneous solution of multiple ports (right-hand sides), benefiting structures with large port counts the most. The AXIEM advanced frequency sweep (AFS) algorithm automatically selects a set of frequency points to simulate, then uses these simulated points to interpolate the S-parameter response for the entire band. In V13, AFS is now faster and more accurate, and generally converges on a solution with fewer frequency points.
Like AXIEM, Analyst V13 offers up to a 50 percent reduction in simulation run times. Major meshing upgrades improve robustness and speed and there is now even easier access to the “Ports Only” solve to access port fields, propagation constants, and port impedances. Analyst is now able to model the effects of surface roughness when a roughness parameter is specified, improving the accuracy of transmission line simulations where surface roughness impacts electrical behavior, such as insertion loss.
In addition, Analyst V13 also introduces new 3D editor functionality and improvements targeting drawing (sketcher) functions and solid object controls, materials and attributes organization in the browser tree, auto-complete for parameter and variable expression, and variable grouping and sorting, to highlight a select few.
Third-Party EM Technologies
The AWR Connected™ family of solutions that link NI AWR software to third-party solutions is now enhanced to further automate the flow of layout data from NI AWR Design Environment into partner EM products. In V13, AWR Connected for EM simulators, which includes ANSYS HFSS, CST, and Sonnet, is more robust and fully bi-directional. After the layout is created in the Microwave Office layout editor, third-party EM tools can readily be selected as the EM simulator of choice (Figure 3) and the resulting dataset is automatically imported back into Microwave Office to tune, optimize, perform yield analysis, and verify results.
Figure 3. A third-party EM simulator can be selected as the EM simulator of choice by the user such that the resulting dataset is automatically imported back into Microwave Office to tune, optimize, perform yield analysis, and verify results.
Circuit/System Simulation and Models/Libraries
Harmonic Balance Technology
Harmonic balance simulation is an essential technology in analyzing RF/microwave nonlinear circuits with active devices (transistors). APLAC, the trade name of NI AWR Design Environment’s high-frequency circuit simulation technology, is seamlessly integrated into both Microwave Office and Analog Office circuit design tools. It has been developed to minimize memory requirements and simulation run times while maintaining accuracy for RF/microwave designs. To address nonlinear devices for communication systems, APLAC now includes a time-variant HB (circuit envelope) simulator capable of addressing circuits excited by non-periodic signal sources such as modulated RF signals. The associated measurements provide the time-varying voltage or current of a particular carrier and the associated spectrum surrounding that carrier. With the added capability of simulating modulated waveforms with circuit envelope, new sources have been added to describe modulated waveforms, such as the ability to specify the IQ data of a modulated signal.
Additionally, the speed and robustness of the APLAC transient (time-domain) simulation engine is enhanced with a new core algorithm and improved time-step algorithm. Other developments include new error control and a transient preset option that can be set to Accurate, Moderate, or Fast. The transient-assisted HB (TAHB) option, used for the digital divider circuits and accurate nonlinear phase-noise measurements of analog and RF applications, can be leveraged in V13 for oscillator analysis by setting the TAHB options to Disabled, Convergence Aid, or Initial Guess.
With time-domain simulations such as transient and circuit envelope, it is necessary to extract a time-domain model for passive devices, S-parameters, and transmission lines. Improvements to the time-domain model in V13 include a better speed-to-accuracy ratio in the extraction of S-parameter data, more robust handling of poor quality data, and more robust passivity enforcement.
For amplifier designs with an existing transistor model, V13 further supports nested source/load pull contours, enabling designers to directly observe changing source and load contours as a function of source and load impedance terminations. This unique capability allows designers to provide a new terminating impedance to either the source or load and directly observe the change to the contours at the other port without having to re-simulate the circuit, thereby eliminating the time-consuming iterative approach to source/load matching.
Design for Communication Systems
Achieving 5G performance is being addressed through developments in several primary areas. One is spectral usage, which includes variations on orthogonal frequency division multiplexing (OFDM) based waveforms that were introduced with LTE release 8 and inter- and intra-band carrier aggregation. Another is enhancing over-the-air (OTA) efficiency with the expansion of multiple-in-multiple-out (MIMO) and beam-steering technologies, and finally, moving to higher frequencies, particularly above 6 GHz and into the millimeter-wave frequency range. New capabilities in V13 better aide system and component designers who face further challenges related to implementing these technologies.
For PA designers, new waveforms and carrier integration will make it more challenging to address linearity and efficiency requirements and to achieve the bandwidth to cover the intra-carrier bandwidths. To help designers address these linearity and efficiency requirements, Visual System Simulator™ (VSS) system design software supports load pull based on digitally-modulated active devices like power transistors to generate constant contours for communication performance metrics such as adjacent channel power ratio (ACPR), error vector magnitude (EVM), and bit error rate (BER) using either measured load-pull data or a nonlinear behavioral model based on measured or simulated circuit/active device data.
Models and Libraries
System and PA simulation for communication applications specific to VSS is further enabled with new libraries and capabilities introduced in V13. The VSS software now provides LTE-Advanced (LTE-A) support for carrier aggregation of intra-band and inter-band component carriers and 5G candidate modulated waveforms (Figure 4) such as filter-bank multicarrier (FBMC), generalized frequency-division multiplexing (GFDM), and filtered orthogonal frequency-division multiplexing (OFDM).
Figure 4. New 5G candidate waveforms and measurements support analysis of digitally modulated nonlinear circuits and communications systems.
Figure 4 • New 5G candidate waveforms and measurements support analysis of digitally modulated nonlinear circuits and communications systems.
These technologies take advantage of faster processing speeds to offer higher data rates and are therefore being considered to replace OFDM download (DL) and single-carrier frequency-division multiple access (SC-FDMA) upload (UL).
Measurements and Results
For sharing and re-using results in subsequent simulations, a new output file measurement feature in VSS writes a compatible nonlinear behavioral model text file that includes information on fundamental input, fundamental output, intermodulation (IM3) products (for two-tone simulations), harmonics (for one-tone simulations), S11, S22, characteristic input and output impedances, and noise figure. In addition, signal heritage information obtained from the RF Inspector (RFI) technology within VSS can be exported to an .xml file.
Even before a simulation is complete, the new marching waveforms feature in V13 begins plotting “real-time” measurement data on defined measurement graphs, giving designers an early preview of simulation results and the opportunity to adjust a design or simulation parameter if there are any issues with the design response or simulation setup.
To help users assess measurement data, two new marker types, auto-search markers and offset markers, are now available. Auto-search markers automatically search for a user-specified feature such as trace maximum and shift along the x-axis to stay aligned with the feature as the trace is updated due to tuning, optimization or other performance goal. Offset markers maintain a specified x or y offset from another marker on the trace. In addition, rich-text notes can now be attached to markers to help document graphs and share insights with fellow designers.
Optimization and Synthesis
Last but by no means least, V13 offers new functionality to accelerate design starts with the addition of synthesis wizards for designing transformers, power dividers, hybrids, mixers, and multipliers based on a given set of user input specifications. Design optimization has been improved with the introduction of genetic algorithm methods that use recombination and selection to rapidly and robustly explore a large number of points randomly distributed over the design space. This results in a more efficient and faster approach to investigating design possibilities and identifying optimum solutions.
NI AWR Design Environment V13 provides new and enhanced innovative solutions in design automation and simulation technology for the advancement of high-frequency electronic products serving the communication and aerospace/defense industries. As component requirements for these applications drive advances in semiconductor, PCB, and multi-chip module integration, NI AWR software offers powerful enhancements in design flow automation and greater speed and accuracy for its circuit/system/EM simulation technologies, enabling device manufacturers and system integrators to meet challenging performance metrics, size, cost, and time-to-market goals.
For more detail on NI AWR Design Environment V13 visit awrcorp.com/whats-new, which provides documentation covering the hundred plus enhancements/additions to this latest release.
About the Author
David Vye serves as Technical Director at AWR Group, NI.
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